1. [Field of the Invention]
The present invention relates to a semiconductor device with a reduced surface field strength type MOS transistor, a method of manufacturing the same semiconductor device, and a semiconductor device with a load driving semiconductor element such as an LDMOS (Lateral Diffused MOS) transistor (which will be referred hereinafter to as an LDMOS), and further an LDMOS (Lateral Double Diffused) transistor such as a power transistor serving as a large-current type switching element.
2. [Description of the Prior Art]
As an N-channel LDMOS there has been known an element with a structure as shown in FIG. 50. As illustrated, this LDMOS has an N-type substrate 1, an N well 2 deposited on the N-type substrate 1, a channel P well 3 formed in the N well 2, an N-type diffused layer 4 formed in the channel P well 3 and a different N-type diffused layer 5 provide in the N well 2. In addition, a gate electrode 7 is located on a substrate surface in a state that a gate oxide film 6 is interposed therebetween while a channel region 8 is formed in a surface area of the channel P well 3 right under the gate electrode 7. In this structure, the N-type diffused layer 4 serves as a source region, the N-type diffused layer 5 acts as a drain region, and the N well 3 under an LOGOS oxide film 9 functions as a drift region. In the illustration, numerals 10 and 11 represent a source electrode and a drain electrode, respectively, numeral 12 designates a diffused layer for taking the electric potential of the channel P well 3, and numeral 13 denotes an inter-layer insulating film.
In the case of such an LDMOS, if the concentration of the N well 2 is heightened in order to reduce the ON resistance to facilitate the current flow, difficulty is encountered to enlarge the depletion layer in the drift region, so that a high breakdown voltage (characteristic bearing a high voltage) becomes unobtainable. On the contrary, if the concentration of the N well 2 falls, although the breakdown voltage improves, the current becomes hard to flow so that the ON resistance increases.
One possible solution of such problems is exemplified by Japanese Patent publication No. 59-24550 and Japanese Unexamined Patent Publication No. 5-267652. The outline of the structure disclosed in these publications is that, as shown in FIG. 51, an N well 2 is formed on a P-type substrate 14. In this case, if the formation of the N well 2 is based on the diffusion, the N well 2 surface shows a high concentration, and hence the flow of the current becomes easy in the N well 2 surface, besides the depletion layer can readily enlarge in the whole N well 2, with the result that a high breakdown voltage is attainable. This LDMOS is called a reduced surface field strength type (RESURF=REduced SURface Field) LDMOS where the dopant concentration in the drift region of the N well 2 is determined to satisfy the so-called RESURF condition as described in the above-mentioned publications.
In the aforesaid reduced surface field strength type LDMOS, the drain electrode 11 and the P-type substrate 14 are in an electrically connected relation to each other, and hence, in cases where as shown in FIG. 52 an L load such as a coil 15 is electrically coupled to the drain electrode 11 so that the L load gets into a driven condition, when the voltage applied to the gate electrode 7 comes into the OFF condition, a reverse voltage of the L load 15 has an influence on the drain electrode 11. This reverse voltage can frequently assume an extremely high value. In this case, since the above-mentioned reduced surface field strength type LDMOS does not take into consideration the current escaping path coping with the reverse voltage, the PN junction between the channel P well 3 and the N well 2 comes into breakdown at the application of the reverse voltage to cause a current to flow from the channel P well 3 through a P+ diffused layer 12 to the source electrode 10 so that the electric potential of the channel P well 3 exceeds the electric potential of the N-type diffused layer 4, with the result that a parasitic (incidental) transistor comprising the N-type diffused layer 4 acting as the emitter, the channel P well 3 serving as the base and the N well 2 functioning as the collector comes into operation to cause a large current to flow through a narrow area in an arrow direction. Because of the occurrence of the large current passing through the narrow area, the elements are easy to heat so that the breakdown of the elements takes place irrespective of a low reverse voltage, thus resulting in impairing the breakdown proof of the elements.
Furthermore, the aforesaid reduced surface field strength type LDMOS is situated on the P-type substrate 14, and hence, in the case that a V-NPN transistor (which will be referred hereinafter to as an NPNTr) superior in current characteristic to a PNP transistor and the aforesaid reduced surface field strength type LDMOS are formed on the same substrate, since an N layer serving as a collector layer in the NPNTr is made to take a deep position, difficulty is actually experienced to form both the transistors on the same substrate. In this case, although, if having the structure as shown in FIG. 50, the LDMOS, together with the NPNTr, can be formed on the same substrate, the compatibility of a high breakdown voltage and a low ON resistance as described before become impossible.
Moreover, there have been proposed various SOI (Silicon On Insulator) structures in which an element area in one main surface side of a semiconductor substrate is divided and separated using an insulating film such as SiO2 to form islands. In this case, elements such as a bipolar transistor and CMOS are formed in the island-like divisions, respectively. The aforesaid power LDMOS is considered to be also formed in the island-like element division. For example, in the case that the LDMOS as shown in FIG. 50 is surrounded by an insulating film, the N-type substrate 1 comes into contact with the insulating film. With this structure, the N-type substrate 1 and the N well 2 becomes common in electric potential to its drain. For this reason, in cases where as shown in FIG. 10A a load is driven by a low side switch type where the load is connected to the power supply side and the LDMOS is coupled to the GND side, in response to the switching of the LDMOS, the drain electric potential varies from the potential of the GND to the potential of the power supply (or more), and the potential of the N-type substrate 1 varies accordingly.
In cases where the element separation is made through the use of the insulating film, since there exists a parasitic capacitor, when the electric potential in the region brought into contact with the insulating film greatly varies, switching noises are propagated up to the other element regions so that the other semiconductor elements can get into malfunction. In the case of the reduced surface field strength type LDMOS as shown in FIG. 51, the P-type substrate 14 comes into contact with the separation insulating film. As illustrated, in order to make the P-type substrate 14 and the source electrode equal in electric potential to each other, the formation of a deep P+ diffused layer for taking the electric potential is necessary. However, in the case that the load is driven by a high side switch type in which as shown in FIG. 10B the LDMOS is connected to the power supply side and the load is coupled to the GND side, in response to the switching of the LDMOS, the source electric potential greatly varies, which can also cause the switching noises.
If, in the SOI structure, elements such as a bipolar transistor and a CMOS of relatively small sizes are formed in the element regions, the aforesaid switching noises does not create a problem. However, in the case of the load driving element such as the LDMOS, the element size increase, thus creating such a problem.
It is therefore an object of the present invention to provide a reduced surface field strength type LDMOS which is capable of preventing the breakdown of elements at channel forming portions even if its drain undergoes a voltage such as the aforesaid reverse voltage.
Another object of this invention is to form a reduced surface field strength type LDMOS and an NPNTr on the same substrate.
A further object of this invention is to suppress the occurrence of the switching noises when a load driving semiconductor element is provided in an insulated and separated element region.
A further object of this invention is to realize a power MOS transistor having a high surge current withstand.
For the first-mentioned purpose, there is provided a semiconductor device having a reduced surface field strength type MOS transistor in which a semiconductor layer (1) of a first conductivity type supports a first well (16) of a second conductivity type which accommodates a second well (2) of a first conductivity type at a shallower position than the first well (16), and further the second well (2) has a source region (4), a channel region (8) and a drain region (5) therein and a gate electrode (7) is disposed on the channel region (8) so that the second well (2) serves as a drift region, wherein, when a voltage for causing the MOS transistor to be in a non-actuating condition is applied to the gate electrode (7) and a high voltage exceeding a given value is exerted to the drain region, a current-carrying path from the second well (2) through the first well (16) and the semiconductor layer (1) takes place.
Furthermore, the source region (4) and the semiconductor layer (1) are set to be equal in potential to each other. In addition, a parasitic bipolar transistor (18) is formed among the second well (2), the first well (16) and the semiconductor layer (1) to establish the current path. Further, a punchthrough occurs between the second well (2) and the semiconductor layer (1) to establish the current path. Still further, a base region (17) is formed to include the source region (4) and to reach the first well (16).
Moreover, there is provided a semiconductor device including a MOS transistor having a source region (4), a channel region (8) and a drain region (5) so that a gate electrode (7) is formed on the channel region and a drift region is set up between the channel region (8) and the drain region (5), wherein a semiconductor layer (1) of a first conductivity type bears a second conductive type first well (16) which in turn accommodates a first conductive type second well (2) at a shallower position than the first well (16), and at least the second well (2) has the drift region and the drain region (5) therein and the source region (4) and the semiconductor region (1) are set to be equal in potential to each other.
According to this invention, the second conductivity type first well and the first conductivity type second well are formed in the first conductivity type semiconductor layer to establish a double-well structure, and the drift region and drain region of the MOS transistor is provided in the second well. In the case that a reverse voltage is applied to the drain region, a current-carrying path is provided in a wide area extending from through the first well and the semiconductor layer. Accordingly, even if such an application of a reverse voltage occurs, this current-carrying path can prevent the breakdown of the elements at the channel formation portions.
For the second-mentioned purpose, there is provided a semiconductor device in which an N-type first semiconductor layer (21a) is divided into first and second element areas so that a reduced surface field strength type MOS transistor (LDMOS) is formed in the first element area while a bipolar transistor (NPNTr) is formed in the second element area in a state that the first semiconductor layer (21a) serves as its collector layer, wherein in the first element area a P-type first well (16) is formed in the first semiconductor layer (21a), an N-type second well (2) is formed in the first well (16) to be shallower than the first well (16) to further accommodate a source region (4), a channel region (8) and a drain region (5), and a gate electrode (7) is located on the channel region (8), so that the reduced surface field strength type MOS transistor is made in a state that the second well (2) acts as a drift region.
Furthermore, an N-type second semiconductor layer (21b) is formed under the first semiconductor layer (21a) and an N-type deep layer (26) is formed which extends from a surface of a substrate to the second semiconductor layer (21b), with the source region (4) and the first semiconductor layer (21a) being set to be equal in potential to each other in such a manner that the potential depends upon the deep layer (26) and the second semiconductor layer (21b).
According to this invention, the P-type first well and the N-type second well are formed in the N-type semiconductor layer to make a double-well structure, thus establishing a reduced surface field strength type MOS transistor. Accordingly, this MOS transistor, together with the NPNTr using the N-type semiconductor layer as the collector layer, can be situated on one substrate.
Still further, in accordance with this invention, there is provided a method of manufacturing a semiconductor device so that in a semiconductor substrate including an N-type semiconductor layer (21a) divided into first and second element areas a reduced surface field strength type MOS transistor (LDMOS) is formed in the first element area while a bipolar transistor (NPNTr) is formed in the second element area, which comprises the steps of performing ion-implantation for the semiconductor layer (21a) to form a P-type first well and an N-type second well (2), performing simultaneous diffusion to form the first well (16) and to form the second well (2) in the first well (16) so that it takes a shallower position than the first well (16), forming a source region (4), a channel region (8) and a drain region (5) within the second well (2), and forming a gate electrode (7) on the channel region (8) to form the MOS transistor (LDMOS) in which the second well (2) serves as a drift region. In addition, the bipolar transistor (NPNTr) is formed in the second element area in a state that the semiconductor layer (21a) acts as a collector layer.
According to this invention, in the manufacturing method of producing the reduced surface field strength type MOS transistor and the NPNTr on the same substrate, the first and second wells are produced by the simultaneous diffusion, with the result that only one mask is required for the formations of the first and second wells.
In the above description, the references within the parentheses signify the corresponding relation to the concrete means in embodiments which will be explained later.
Still further, in accordance with this invention, there is provided a semiconductor device in which a load driving semiconductor element is formed in a insulated and separated element region and an electric potential fixing region for surrounding the semiconductor element is defined between the semiconductor element and an insulating film. Because of surrounding the semiconductor element by the electric potential fixing region, the electric potential variation at the load driving is suppressible to control the occurrence of the switching noises.
In addition, there is provided a semiconductor device in which, when a reverse voltage is applied to a drain region, a current-carrying path is formed to extend from a second well through a first well, a first semiconductor layer and an electric potential fixing region. The formation of this current-carrying path can prevent the breakdown of the elements in the channel formation section at the application of the reverse voltage. Further, the first well is set to be equal in electric potential to the source. This enables further suppressing the occurrence of the switching noises at the electric potential variation.
Furthermore, in the case that an MOS transistor is used for the high side switch type, the electric potential fixing region is connected to the power supply, and when the MOS transistor is used for the low side switch type, the electric potential fixing region is coupled to the ground. In this case, if the electric potential fixing region is made to be selectively coupled to one of the power supply and the ground, one of the low side switch type and the high side switch type can freely undergo selection.
Moreover, in accordance with an aspect of the present invention, on a semiconductor substrate a surface portion of a second conductive well region adjacent to source and drain cells is connected as a surge current absorption section to a drain terminal, and a surface portion of a first conductive well region adjacent to the surge current absorption section is connected as a surge current draw (extraction) section to a source terminal, wherein the resistance between the surge current absorption section and the surge current draw section is set to be lower than the resistance between the source and drain cells and the surge current absorption section. Whereupon, as shown in FIG. 51 the surge current brought from the output terminal (drain) flows laterally through a parasitic diode D3 produced by both the well regions and discharges to the source terminal side after passing through the first conductive well region (the surge current draw section). Thus, the surge current does not flow in the source region present on a surface of the source and drain cells so that the protection of a MOS channel section is possible to enhance the withstand against the surge such as static electricity, with the result that a power MOS transistor with a high surge withstand is realizable.
In addition, if a second conductive impurity diffusion region is formed in the surge current absorption section of the second conductive well region with a higher impurity concentration than that of the second conductive well region and at a position deeper than that of a second conductive impurity diffusion region in a drain cell so that a break voltage lower than an element breakdown voltage is obtainable, at a voltage lower than the element breakdown voltage the surge current can discharge to the source terminal side through the first conductive well region.
In accordance with another aspect of the present invention, second conductive deep semiconductor regions extending in a depth direction from the surface side of a semiconductor substrate are made to scatter in the interior of a source and drain cell formation region so that the deep semiconductor regions define a surge current path. With this structure, as shown in FIG. 20 the surge current coming from the output terminal (drain) discharges through the scattering deep semiconductor regions (226a, 226b, 226c) in addition to the parasitic diode due to both the well regions. That is why all the surge currents dispersedly or separately flow without gathering at the drain, and hence no surge current flow in the source region present on the surface, thus protecting the MOS channel section to improve the withstand against the surge such as static electricity. This allows a power MOS transistor with a high surge withstand.
In accordance with a different aspect of the present invention, a second conductive semiconductor buried layer is formed under a first conductive well region in a semiconductor substrate and further second conductive deep semiconductor regions extending in the depth direction from the surface side of the semiconductor substrate and reaching the semiconductor buried layer are made to scatter in the interior of source and drain cells so that a surge current path is defined by the semiconductor buried layer and the dep semiconductor regions. With this structure, as shown in FIG. 17 the surge current introduced from the output terminal (drain) flows vertically through a parasitic transistor created by both the well regions and the semiconductor substrate and gets out through the semiconductor buried layer (207) and the deep semiconductor regions (226a, 226b, 226c). Moreover, as shown in FIG. 20 the surge current brought from the output terminal (drain) discharges through the scattering deep semiconductor regions (226a, 226b, 226c) in addition to the parasitic diode developed by both the well regions, so that the surge current dispersedly flows without all concentrating in the drain. That is why no surge current flows in the source region in the surface, and the protection of the MOS channel section is possible, thus enhancing the withstand against the surge such as static electricity, which realizes a power MOS transistor with a high surge withstand.
In addition, the aforesaid deep semiconductor regions are disposed around the source and drain cell formation region grouped into a plurality of blocks. Further, the deep semiconductor regions are disposed in the form of islands within the source-drain cell formation region. Still further, preferably, the source and drain cell formation region interposed between the deep semiconductor regions is less than 200 mm in width. Besides, the deep semiconductor regions are made to have plane structures producing band (or strip)-like configurations, and are provided within the source and drain cell formation region to extend in parallel to each other at a given interval.